Type Data tra c Replacement tra c Coherence tra cUMA

Shared-bus multiprocessors represent a mainstream of accepted and commercially viable computer systems. However, as microprocessors become faster and demand more bandwidth, the already limited scalability of shared-bus decreases even further. As an eeort, not a mutually exclusive but rather a complementary to developing better backplane bus, this paper considers adapting distributed shared-memory (DSM) architec-tures to improve traditional shared-bus designs. We consider two well-known DSM architectures, namely cache-coherent NUMA (Non-Uniform Memory Architecture) and COMA (Cache-Only Memory Architecture). Even with modest number of processors found in shared-bus multiprocessors, these DSM architectures, mainly proposed for large-scale scalable multiproces-sors, may prove to be useful in reducing global bus traac. Based on a split-protocol shared-bus model, we compare potential performance of these DSM architec-tures with a traditional shared-memory shared-bus architecture. Our study shows that COMA provides excellent opportunity of signiicantly reducing bandwidth requirement for the bus while cache-coherent NUMA provide little improvement.